A block diagram of a conventional power supply apparatus is shown in FIG. 17. In this block diagram, an output voltage Vo is negatively fedback, and is subtracted from a reference voltage Vref, and its calculation result (Vref−Vo) is input to a transfer function PID corresponding to a PID controller. An output of this transfer function PID is added with the feed forward reference voltage Vref, and the addition result is input to a transfer function PW corresponding to a power converter circuit. An output of the transfer function PW is input to a transfer function LC corresponding to an LC filter and the like, and an output of the transfer function LC is the output voltage Vo. Incidentally, the PID controller is a controller combining a proportional (P) element, integral (I) element and differential (D) element. Conventionally, to stably control a system, both of the gain margin and the phase margin were needed to be secured in the Bode diagram of a loop transfer function consisting of the transfer function PID of the PID controller, transfer function PW corresponding to the power converter circuit, and transfer function LC of the LC filter and the like. FIG. 18 is a Bode diagram of the loop transfer function of a conventional power supply apparatus, and the upper diagram shows the frequency characteristic of the gain and the lower diagram shows the frequency characteristic of the phase. The phase margin is phase width from −180 degrees at a frequency at which the gain becomes 0 dB on the Bode diagram as shown in FIG. 18. The phase margin from 45 to 60 degrees or more is usually needed. Moreover, as shown in FIG. 18, the gain margin is gain width from 0 dB on a minus side at a frequency at which the phase is delayed up to −180 degrees. The gain margin of 6 dB or more is needed usually.
Specifically, following designs are performed under such a stability condition. That is, though the integral element is applied from the low frequency range to solve the steady-state deviation, since the LC filter to be controlled is a second order lag system and the phase delay of 180 degrees occurs at frequencies equal to or higher than the resonance frequency, the application of the integral element is terminated at a frequency that is lower than the resonance frequency, so that the large phase delay does not occur at frequencies equal to or higher than the resonance frequency. And, to secure the phase margin and the gain margin, the differential element is applied from the vicinity of the resonance frequency. However, in such a conventional power supply apparatus, since the controller is designed while securing both of the gain margin and phase margins, it is difficult to achieve the high gain and high speed response.
Moreover, for example, U.S. Pat. No. 5,844,403 discloses a circuit as shown in FIG. 19. That is, a power supply apparatus shown in FIG. 19 is composed of a power converter 1002, input power supply 1003, smoothing circuit 1004, load 1005, and controller 1000. The controller 1000 has resistors R11 to R17, capacitors C11 and C12 and an amplifier 1011. One terminal of the resistor R11 and resistor R14 is respectively connected to a positive polarity side of the load 1005, another terminal of the resistor R11 is connected to a negative input terminal of the amplifier 1011 and one terminal of the resistors R12 and R13, and another terminal of the resistor R14 is connected to one terminal of the resistors R15 and R16 and capacitor C12. Another terminal of the resistors R12 and R15 and capacitor C12 is grounded. Moreover, another terminal of the resistor R13, whose one terminal is connected to the resistors R11 and R12 and the negative input terminal of the amplifier 1011, is connected to one terminal of the capacitor C11. Another terminal of the capacitor C11 is connected to an output terminal of the amplifier 1011 and a first input terminal of a comparator 1021 in the power converter 1002. Another terminal of the resistor R16, whose one terminal is connected to the resistors R14 and R15 and the capacitor C12, is connected to a positive input terminal of the amplifier 1011 and one terminal of the resistor R17. Another terminal of the resistor R17 is connected to a positive terminal of a reference voltage source Vr. A negative terminal of the reference voltage source Vr is grounded.
The power converter 1002 is composed of a comparator 1021, triangular wave generator 1022, gate driving circuit 1023, MOSFET 1024, and choke coil 1025. As described above, the first input terminal of the comparator 1021 is connected to the output terminal of the amplifier 1011 and the capacitor C11, and a second input terminal of the comparator 1021 is connected to the triangular wave generator 1022. An output terminal of the comparator 1021 is connected to the gate driving circuit 1023, and an output terminal of the gate driving circuit 1023 is connected to the gate of the MOSFET 1024. The source of the MOSFET 1024 is grounded, and the drain thereof is connected to one terminal of the choke coil 1025 and the anode of the diode 1041 in the smoothing circuit 1004. Another terminal of the choke coil 1025 is connected to a positive terminal of the power source 1003. A negative terminal of the power source 1003 is grounded.
The smoothing circuit 1004 is composed of a diode 1041 and capacitor 1042. As described above, the anode of the diode 1041 is connected to the drain of the MOSFET 1024 and one terminal of the choke coil 1025, and the cathode thereof is connected to one terminal of the capacitor 1042 and a positive polarity side terminal of the load 1005. Another terminal of the capacitor 1042 is grounded. The positive polarity side terminal of the load 1005 is connected with the cathode of the diode 1041 and one terminal of the capacitor 1042, and a negative polarity side terminal thereof is grounded.
The controller 1000 generates a control signal u from the output voltage Vo and the reference voltage Vr of the reference voltage source. The control signal u is compared in the comparator 1021 with the output of the triangular wave generator 1022, and the output of the comparator 1021 drives the MOSFET 1024 through the gate driving circuit 1023. After being converted by the MOSFET 1024 that is turned on or off according to the output of the comparator 1021, and the choke coil 1025, and being smoothed by the smoothing circuit 1004, the input voltage of the power source 1003 is output to the load 1005 as the output voltage Vo.
Here, the transfer function of the controller 1000 is as follows:                                                         b              2                        ⁢                          s              2                                +                                    b              1                        ⁢            s                    +                      b            0                                    s          ⁡                      (                          s              +                              a                1                                      )                                              (        1        )            
Incidentally, each coefficient b0, b1, b2, and a is represented as follows:             a      1        =                  1                  C          12                    ⁢              (                              1                          R              14                                +                      1                          R              15                                +                      1                                          R                16                            +                              R                17                                                    )                        b      0        =                            1                                    C              11                        ⁢                          C              12                        ⁢                          R              11                                      ⁢                  (                                    1                              R                14                                      +                          1                              R                15                                      +                          1                                                R                  16                                +                                  R                  17                                                              )                    -                                    R            17                                              C              11                        ⁢                          C              12                        ⁢                                          R                14                            ⁡                              (                                                      R                    16                                    +                                      R                    17                                                  )                                                    ⁢                  (                                    1                              R                11                                      +                          1                              R                12                                              )                                b      1        =                  1                              C            11                    ⁢                      R            11                              +                                    R            13                                              C              12                        ⁢                          R              11                                      ⁢                  (                                    1                              R                14                                      +                          1                              R                15                                      +                          1                                                R                  16                                +                                  R                  17                                                              )                    -                                    R            17                                              C              12                        ⁢                                          R                14                            ⁡                              (                                                      R                    16                                    +                                      R                    17                                                  )                                                    ⁢                  {                                                    (                                                      1                                          R                      11                                                        +                                      1                                          R                      12                                                                      )                            ⁢                              R                13                                      +            1                    }                                b      2        =                   ⁢                  R        13                    R        11            
The feature of this power supply apparatus is that the root of the numerator of the equation (1) is an imaginary number, and it is said that the stable control is enabled by raising the phase up to a prescribed range at a frequency at which the gain is smallest. However, since a lot of resistors and capacitors exist in the circuit shown in FIG. 19, there is a problem that it is difficult to determine each circuit constant while making the root of the numerator of the equation (1) an imaginary number, and the circuit design cannot be easily carried out. Incidentally, a related patent of this patent is U.S. Pat. No. 5,583,752.
Thus, in the background art, the power supply apparatus enabling the high speed response with a little number of circuit constant settings was not able to be achieved.